The invention relates to testing integrated circuits, and, more particularly, to a method and apparatus for programmably selecting and applying weights, on a per channel basis, to test patterns within a logic built-in self-test (LBIST) structure.
Logic built-in self-test (LBIST) is used to test the integrated circuit logic of high-end servers and computers. LBIST is used at all levels of test including: integrated circuit, MCM, and system. Conceptually, the LBIST approach is based on the realization that much of a circuit tester""s electronics is semi conductor-based, just like the devices under test, and that many of the challenges and limitations in testing lie in the interface to the Device Under Test (DUT). The LBIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the devices under test and eliminate the complex interfacing. One of the major advantages LBIST has over other means of testing logic is that the operation of the test is self-contained. All of the circuitry required to execute the test at-speed is contained within the integrated circuit. Very limited external controls are needed, so LBIST can be run at all levels of packaging (wafer, TCA, module and system) without requiring expensive external test equipment.
LBIST utilizes what is commonly referred to as Self-Test Using Multiple Signal Registers and Pseudo-Random Pattern Generators (STUMPS) architecture. The major components of LBIST include: a pseudo-random pattern generator (PRPG) used to generate the test patterns; a multiple input signature register (MISR) to compress the test results; and the self-test control macro (STCM) that is used to apply the clocks and controls to the PRPG, MISR and system logic to perform the test. The PRPG applies test data to the system logic via multiple parallel scan chains, which are connected between the PRPG and MISR.
One of the limitations of LBIST is the maximum achievable test coverage. Because the PRPG is implemented using a linear feedback shift register (LFSR) that generates random patterns (50% chance of being a 0 or a 1), certain random resistant structures are difficult, if not impossible, to test. Examples would be very wide AND gates or OR gates where the probability of all inputs being a 1 in the case of an AND or all inputs being a 0 in the case of an OR would be very small. Typically LBIST test coverage peaks at around 96%. The remaining faults must be tested by some other means of logic test, either weighted random pattern test (WRPT), deterministic test, or a combination of both.
Weighting is a technique where patterns can be biased towards a 0 or 1 state by ANDing or ORing multiple bits of an LFSR together. Instead of there being a 50% chance of a 0 or a 1, the odds of a 0 or 1 are weighted to increase the probability of one or the other occurring. For example, if 3 random bits are ORed together, the resultant output has a xe2x85x9e chance of being a 1. Conversely, if 4 random bits are ANDed together, the output has a {fraction (1/16)} chance of being a 1. This weighting technique can be used to test random resistant structures such as large AND or OR structures. A drawback in the current technology is that WRP and deterministic patterns must be applied from a tester and therefore they cannot be applied at higher levels of packaging.
Random resistant fault analysis (RRFA) programs provide users with information about the presence of clusters of faults in the circuit that are difficult to test with random patterns. Testers can use this information to determine the best way to improve random pattern testability. Typically, test data is weighted to account for fault clusters based on the output of the RRFA program.
A previous approach to weighting without the use of external testing equipment required the assignment of hard-coded weights (xe2x85x9, xc2xc, xc2xd, xc2xe, xe2x85x9e, etc.) to the scan chains based on the weighting requirements. There are problems associated with this method of assigning weights. First, logic blocks must be pre-assigned to scan chains and typically, weight analysis is not completed early enough in the design process to make this assignment. Also, a single logic block may have two or more effective weight conditions. Assigning the logic block to a hard-coded weighted channel would only cover one of these effective weight conditions.
An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistance fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.